Image conversion device

ABSTRACT

It is an object of the present invention to simultaneously perform input or output of picture signals for a plurality of components. An image data input interface (310) is capable of input of picture signals (Pm) of three components at its maximum. For example, when picture signals (Pm) of three components are inputted, a clock divider (410) supplies a 1/3 divided signal of a clock signal (CLK) to the image data input interface (310) on the basis of a selection signal (SEL). In the image date input interface (310), the picture signals (Pm) of three components are simultaneously inputted in synchronization with the 1/3 divided signal and they are sent out to a discrete cosine transform unit (4) in synchronization with the clock signal (CLK). The component to which the sent picture signals (Pxy) belong sequentially changes for every 8×8 picture elements. It has the effect of simultaneously performing input or output of picture signals for a plurality of components while matching with operation of a coding device unit is maintained.

This application is a Continuation of application Ser. No. 08/404,296,filed on Mar. 14, 1995, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to image conversion devices such as imagecompression devices, image expansion devices, or combinations thereof.

2. Description of the Background Art

FIG. 16 is a block diagram showing the structure of a conventional imagecompression device. This image compression device is made to realizeimage compression based on the so-called "JPEG algorithm" which isproposed by the JPEG (Joint Photographic Expert Group) aiming fornormalization of the color still image coding system.

For each of picture elements arranged in a matrix along two directionsperpendicular to each other on an image, picture signals Pm (m=0, 1, . .. ) which represent its density, luminance, etc. are sequentiallyprovided as inputs to an image data input interface 3 of this device. Asingle picture signal Pm is comprised of 8 bits to represent density ofa single picture element at 256 gradations. This picture signal Pm issequentially inputted for every 8 bits to the image date input interface3 from an external device through an image data input terminal 13 of8-bit width in synchronization with clock signal CLK which is a periodicpulse train inputted from a clock input terminal 1.

The image data input interface 3 divides the train of the inputtedpicture signals Pm (m=0, 1, . . . ) for each block where 8×8 (=64)picture elements are arranged in a matrix along the two perpendicularscanning directions on the image and outputs them to a discrete cosinetransform unit 4 on the next stage. That is to say, for each block,picture signals Pxy (x, y=0 to 7) representing density of each pictureelement in that block are sequentially sent from the image data inputinterface 3 to the discrete cosine transform unit 4 in synchronizationwith the clock signal CLK.

In the discrete cosine transform unit 4, two-dimensional discrete cosinetransform is applied to 64 Pxy (x, y=0 to 7) in synchronization with theclock signal CLK. The 64 discrete cosine transform coefficients(referred to as "DCT coefficient" hereinafter) Suv (u, v=0 to 7)obtained by the discrete cosine transform are sequentially sent from thediscrete cosine transform unit 4 to a zig-zag conversion unit 5 on thenext stage in synchronization with the clock signal CLK.

In the zig-zag conversion unit 5, the DCT coefficients Suv (u, v=0 to 7)are rearranged from the order along rows and columns of matrix with thearranged DCT coefficients Suv (u, v=0 to 7) into the so-called zig-zagorder. The DCT coefficients Sij (i, j=0 to 7) rearranged into thezig-zag order are then sequentially sent to a quantization unit 6 fromthe zig-zag conversion unit 5 in synchronization with the clock signalCLK.

In the quantization unit 6, the 64 DCT coefficients Sij (i, j=0 to 7)are quantized with step sizes which differ for each coefficient position(values of i, j) using a quantization table 7. That is to say, 64coefficients Qij (i, j=0 to 7) defining step size of each coefficientposition are previously stored in the quantization table 7, and thequantization unit 6 performs division of the DCT coefficient Sij withthe coefficient Qij and makes a quotient thereof integer to obtainquantization coefficients Rij (i, j=0 to 7). This processing isperformed in synchronization with the clock signal CLK. As a result, theobtained quantization coefficients Rij (i, j=0 to 7) are sent from thequantization unit 6 to a Huffman coding unit 8 on the next stage insynchronization with the clock signal CLK.

In the Huffman coding unit 8, referring to a code table 9, coding basedon the Huffman coding system is applied to each of the quantizationcoefficients Rij (i, j=0 to 7). Information for performing the Huffmancoding is previously stored in the code table 9, on the basis of whichinformation the Huffman coding unit 8 converts the quantizationcoefficients Rij (i, j=0 to 7) into a train of coded signals Hn (n=0, 1.. . ) based on the Huffman coding system. This processing is performedin synchronization with the clock signal CLK. As a result, the codedsignals Hn (n=0, 1, . . . ) are sent in synchronization with the clocksignal CLK from the Huffman coding unit 8 to an external device such asa storage device for storing the coded signals.

The clock signal CLK is sent to an external device for inputting thepicture signals Pm (m=0, 1, . . . ) to the image data input terminal 13thorough a clock output terminal 11. This synchronizes operation of theexternal device with the clock signal CLK to enable input of picturesignals Pm (m=0, 1, . . . ) to the image date input terminal 13 insynchronization with the clock signal CLK.

In comparison for each block, the signal size of the coded signals Hn(n=0, 1, . . . ) is made smaller than the signal size of the 64 picturesignals Pxy (x, y=0 to 7). That is, this device realizes compression ofthe picture signals.

To reproduce the image, the picture signals must be reverselyreconstructed from the coded signals Hn which are compressed picturesignals. For this aim, a conventional image expansion device making apair with the device shown in FIG. 16 is used. FIG. 17 is a blockdiagram showing structure of this image expansion device.

As shown in FIG.17, the coded signals Hn (n=0, 1, . . . ) are sent inthe order of a Huffman decoding unit 28, a non-quantization unit 26, aninverse zig-zag conversion unit 25, an inverse discrete cosine transformunit 24 and an image data output interface 23 in synchronization withthe clock signal CLK inputted from the clock input terminal 1. The imagedate output interface 23--the Huffman decoding unit 28 constituting theimage expansion device respectively perform processings reverse to theprocessings in the image data input interface 3--the Huffman coding unit8 constituting the image compression device. The code table 9 in theimage compression device is referred to in the Huffman decoding unit 28and the quantization table 7 is referred to in the non-quantization unit26.

Accordingly, inputted coded signals Hn (n=0, 1, . . . ) are sequentiallysubjected to processings reverse to those in the image compressiondevice. As a result, reconstructed picture signals Pm (m=0, 1, . . . )are provided as outputs from the image date output interface 23.However, due to the processing made in the quantization unit 6 of theimage compression device, the reconstructed picture signals Pm (m=0, 1,. . . ) are not necessarily completely the same as the picture signalsPm (m=0, 1, . . . ) before compressed, but they have been changed in therange where effective image quality is not degraded. That is to say, thesystem of image compression and image expansion based on the JPEGalgorithm belongs to the category of non-reversible system.

The clock signal CLK is sent out to an external device to which thepicture signals Pm (m=0, 1, . . . ) are inputted through the clockoutput terminal 11. The external device is sequentially supplied withthe picture signals Pm (m=0, 1, . . . ) from the image data outputinterface 23 in synchronization with the clock signal CLK.

As the conventional image compression device and the image expansiondevice are constituted as described above, both of the input of thepicture signals Pm from the external device and the output thereof tothe external device must be made in synchronization with the clocksignal CLK. Accordingly, if the frequency of the clock signal CLK ishigh and the speed of processings in the device is high, input andoutput of the picture signals Pm in the external device must beperformed at high speed, too. That is to say, it has been a problem thatinput interface or output interface of the picture signals Pm providedin the external device must operate at high speed in synchronizationwith the clock signal CLK.

Furthermore, when simultaneously compressing or expanding picturesignals Pm of a plurality of components corresponding to a plurality ofcolor components represented by trichromatic components of the RGB (Red,Green, Blue) calorimetric system, for example, input must be made foreach component unit, resulting in a problem that a buffer or the likemust be additionally provided outside of the device.

SUMMARY OF THE INVENTION

According to the present invention, an image conversion device forcoding a train of picture signals representing an image for each blockin the image comprises coding means sequentially receiving the picturesignals as inputs in synchronization with a clock signal and convertingthe picture signals into coded signals in the block unit, dividing meansfor dividing the clock signal to generate a divided signal having aperiod longer than that of the clock signal, and interface meanssequentially receiving the picture signals as inputs in synchronizationwith the divided clock signal and sequentially outputting the picturesignals to the coding means in synchronization with the clock signal.

According to the present invention, the picture signals are inputted tothe interface means from outside in synchronization with the dividedclock signal having its period longer than that of the clock signal andthe inputted picture signals are inputted to the coding means insynchronization with the clock signal so that they agree with theoperation of the coding means. That is to say, the device of theinvention operates in matching with an external device having adifferent speed of output of the picture signals than the processingspeed of the coding means.

Preferably, in the image conversion device of the present invention, theinterface means simultaneously receives as inputs picture signalsbelonging to a plurality of components identical in number to a ratiobetween the period of the divided clock signal and the period of theclock signal in synchronization with the divided clock signal, and itsequentially outputs the picture signals to the coding means insynchronization with the clock signal, with the component to which theoutputted picture signal belongs sequentially changed for each of theblocks.

According to the present invention, the picture signals belonging to aplurality of components identical in number to the ratio between theperiod of the divided clock signals and the period of the clock signalare simultaneously inputted in synchronization with the divided clocksignals. The picture signals are outputted to the coding means insynchronization with the clock signal and the component is sequentiallychanged in a block unit while they are outputted. Accordingly, coding ofthe picture signals of the respective components is accomplished in thecoding means. That is to say, in the device of the invention, picturesignals of a plurality of components can be inputted simultaneouslywhile matching with operation of the coding means is maintained.

Preferably, in the image conversion device of the present invention, thedividing means is capable of generating a divided clock signal having aperiod which is an arbitrary natural number, being not more than apredetermined plural number, times the period of the clock signal, theinterface means is capable of simultaneous input of the picture signalsbelonging to an arbitrary number, being not more than the predeterminedplural number, of component(s) in synchronization with the divided clocksignal generated by the dividing means, and it sequentially outputs thepicture signals to the coding means in synchronization with the clocksignal, and the components to which the outputted picture signals belongcan be sequentially changed for each of the blocks, the device furthercomprises control means, and the control means causes the dividing meansto selectively generate a divided clock signal according to the numberof the component(s) inputted to the interface means, the divided clocksignal having a period which is the number of the component(s) times theperiod of the clock signal.

According to the present invention, the number of components inputted tothe interface means is variable, and the dividing means can produceplural kinds of divided clock signals. Furthermore, a divided clocksignal corresponding to the number of inputted components is selected bythe control means. Accordingly, in the device of the invention, picturesignals of an unfixed number of component(s) in a certain range can beinputted simultaneously while maintaining matching with operation of thecoding means.

In another aspect of the present invention, an image conversion devicefor decoding coded signals obtained by coding a train of picture signalsrepresenting an image for each block in the image comprises decodingmeans for converting the coded signals into a train of the picturesignals in the block unit in synchronization with the clock signal andsequentially outputting the train of picture signals, dividing means fordividing the clock signal to generate a divided clock signal having aperiod longer than that of the clock signal, and interface meanssequentially receiving as inputs the picture signals from the decodingmeans in synchronization with the clock signal and sequentiallyoutputting the picture signals in synchronization with the divided clocksignal.

According to the device of the present invention, the picture signalsobtained by decoded in the decoding means are inputted to the interfacemeans in synchronization with the clock signal. Further, the picturesignals are externally outputted from the interface means insynchronization with the divided clock signal having a period longerthan that of the clock signal. Accordingly, matching can be obtainedwith an external device having different speed of input of picturesignals than the processing speed of the decoding means.

Preferably, in the image conversion device of the present invention, theinterface means sequentially receives the picture signals as inputs fromthe decoding means in synchronization with the clock signal, portionsout the inputted picture signals to a plurality of components identicalin number to a ratio between the period of the divided clock signal andthe period of the clock signal for each block, and it simultaneouslyoutputs the picture signals belonging to the respective components insynchronization with the divided clock signal.

According to the device of the present invention, while the picturesignals are sequentially inputted from the decoding means insynchronization with the clock signal, the inputted picture signals areportioned out for each block to a plurality of components identical innumber to the ratio between the period of the divided clock signal andthe period of the clock signal, and further, the picture signalsbelonging to the respective components are simultaneously outputted insynchronization with the divided clock signal. That is, in the device ofthe invention, decoding of the coded signals into the picture signals ofthe respective components and simultaneous output of picture signals ofthe plurality of components can be realized in matching with each other.

Preferably, in the image conversion device of the present invention, thedividing means is capable of generating a divided clock signal having aperiod which is an arbitrary natural number, being not more than apredetermined plural number, times the period of the clock signal, theinterface means sequentially receives the picture signals as inputs fromthe decoding means in synchronization with the clock signal and it canportion out the inputted picture signals to an arbitrary number, beingnot more than the predetermined plural number, of component(s) for eachof the blocks, and it is also capable of simultaneously outputting thepicture signals belonging to the respective components insynchronization with the divided clock signal produced by the dividingmeans, the device further comprises control means, and the control meanscauses the dividing means to selectively produce a divided clock signaldepending on the number of the component(s) outputted from the interfacemeans, the divided clock signal having a period which is the number ofthe component(s) times the period of the clock signal.

According to the device of the present invention, the number ofcomponents outputted by the interface means is variable, and thedividing means can produce plural kinds of divided clock signals.Furthermore, a divided clock signal corresponding to the number ofoutputted components is selected by the control means. Accordingly, inthe device of the invention, picture signals of an unfixed number ofcomponent(s) in a certain range can be outputted simultaneously whilemaintaining matching with operation of the decoding means.

The present invention is also directed to an image conversion devicecapable of coding a train of picture signals representing an image foreach block in the image and capable of reversely decoding the codedsignals into the picture signals. According to the present invention,the image conversion device comprises coding means sequentiallyreceiving the picture signals as inputs in synchronization with a clocksignal and converting the picture signals into coded signals in theblock unit, dividing means for dividing the clock signal to generate adivided clock signal having a period longer than that of the clocksignal, first interface means sequentially receiving the picture signalsas inputs in synchronization with the divided clock signal andsequentially outputting the picture signals to the coding means insynchronization with the clock signal, decoding means for converting thecoded signals into a train of the picture signals in the block unit insynchronization with the cock signal and sequentially outputting thetrain of the picture signals, and second interface means sequentiallyreceiving the picture signals as inputs from the decoding means insynchronization with the clock signal and sequentially outputting thepicture signals in synchronization with the divided clock signal.

According to the device of the present invention, the picture signalsare inputted to the first interface means from outside insynchronization with the divided clock signal with a period longer thanthat of the clock signal and the inputted picture signals are inputtedto the coding means in synchronization with the clock signal so as toagree with operation of the coding means. The picture signals decodedand obtained in the decoding means are inputted to the second interfacemeans in synchronization with the clock signal. Furthermore, the picturesignals are outputted to outside from the second interface means insynchronization with the divided clock signal with a period longer thanthat of the clock signal. That is, the device of the present inventionoperates in matching with an external device having a different speed ofoutput or input of picture signals than the processing speed of thecoding means or the decoding means.

Preferably, in the image conversion device of the present invention, thefirst interface means simultaneously receives as inputs picture signalsbelonging to a plurality of components identical in number to a ratiobetween the period of the divided clock signal and the period of theclock signal in synchronization with the divided clock signal, andsequentially outputs the picture signals to the coding means insynchronization with the clock signal, and it sequentially changes thecomponent to which the outputted picture signals belong for each of theblocks, and the second interface means sequentially receives the picturesignals as inputs from the decoding means in synchronization with theclock signal, portions out the inputted picture signals to a pluralityof components identical in number to a ratio between the period of thedivided clock signal and the period of the clock signal for each of theblocks, and it simultaneously outputs the picture signals belonging tothe respective components in synchronization with the divided clocksignal.

According to the device of the present invention, while the picturesignals belonging to a plurality of components identical in number tothe ratio between the period of the divided clock signal and the periodof the clock signal are simultaneously inputted in synchronization withthe divided clock signal, the picture signals are outputted to thecoding means in synchronization with the clock signal and the componentis sequentially changed in a block unit while they are outputted. At thesame time, while the picture signals are sequentially inputted from thedecoding means in synchronization with the clock signal, the inputtedpicture signals are portioned out for each block to a plurality ofcomponents identical in number to the ratio between the period of thedivided clock signal and the period of the clock signal, and further,the picture signals belonging to the respective components aresimultaneously outputted in synchronization with the divided clocksignal. That is, in the device of the invention, coding or decoding inthe coding means or the decoding means and simultaneous input or outputof picture signals of a plurality of components can be realized inmatching with each other.

Preferably, in the image conversion device of the present invention, thedividing means is capable of producing a divided clock signal having aperiod which is an arbitrary natural number, being not more than apredetermined plural number, times the period of the clock signal, thefirst interface means is capable of simultaneous input of the picturesignals belonging to an arbitrary number, being not more than thepredetermined plural number, of component(s) in synchronization with thedivided clock signal produced by the dividing means, and it sequentiallyoutputs the picture signals to the coding means in synchronization withthe clock signal, and it can sequentially change the component to whichthe outputted picture signals belong for each of the blocks, the secondinterface means simultaneously receives the picture signals as inputsfrom the decoding means in synchronization with the clock signal, and itcan portion out the inputted picture signals to an arbitrary number,being not more than the predetermined plural number, of component(s) foreach of the blocks, and it can simultaneously output the picture signalsbelonging to the respective components in synchronization with thedivided clock signal produced by the dividing means, the device furthercomprises control means, and the control means causes the dividing meansto selectively produce a divided clock signal according to the number ofthe component(s) inputted to the first interface means or the number ofthe component(s) outputted from the second interface means, the dividedclock signal having a period which is the number of the component(s)times the period of the clock signal.

According to the device of the present invention, the number ofcomponents inputted to the first interface means is variable, and thedividing means can produce plural kinds of divided clock signals.Furthermore, a divided clock signal corresponding to the number ofinputted components is selected by the control means. At the same time,the number of components outputted by the second interface means isvariable, and the dividing means can produce plural kinds of dividedcontrol signals. Furthermore, a divided clock signal corresponding tothe number of outputted components is selected by the control means.That is to say, in the device of the invention, picture signals of anunfixed number of component(s) in a certain range can be inputted oroutputted simultaneously while maintaining matching with operation ofthe coding means or the decoding means.

Accordingly, it is an object of the present invention to provide animage conversion device which can perform input or output of picturesignals simultaneously for a plurality of components without requiringany buffer additionally provided and which can obtain matching with anexternal device with different speeds of input or output of picturesignals.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an image compression device according tothe first preferred embodiment of the present invention.

FIG. 2 is a schematic block diagram of an image compression deviceaccording to the preferred embodiment of the present invention.

FIG. 3 is a schematic block diagram of an image expansion deviceaccording to the preferred embodiment of the present invention.

FIG. 4 is a schematic block diagram of an image conversion deviceaccording to the preferred embodiment of the present invention.

FIG. 5 is a block diagram of the image date input interface of the firstpreferred embodiment of the present invention.

FIG. 6 is a description diagram showing operation of the RAM of thefirst preferred embodiment of the present invention.

FIG. 7 is a timing chart of the control signals in the image compressiondevice of the first preferred embodiment of the present invention.

FIG. 8 is a block diagram of an image data input interface according tothe second preferred embodiment of the present invention.

FIG. 9 is a timing chart of the control signals in the image compressiondevice according to the second preferred embodiment of the presentinvention.

FIG. 10 is a block diagram of an image expansion device according to thethird preferred embodiment of the present invention.

FIG. 11 is a block diagram of the image data output interface accordingto the third preferred embodiment of the present invention.

FIG. 12 is a block diagram of an image compression device according tothe fourth preferred embodiment of the present invention.

FIG. 13 is a block diagram of an image compression device according tothe fifth preferred embodiment of the present invention.

FIG. 14 is a block diagram of an encoder according to the sixthpreferred embodiment of the present invention.

FIG. 15 is a block diagram of a decoder according to the sixth preferredembodiment of the present invention.

FIG. 16 is a block diagram of a conventional image compression device.

FIG. 17 is a block diagram of a conventional image expansion device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 1. Outline of the Device of thePreferred Embodiment

Before starting a detailed description of the preferred embodiments ofthe present invention, the outline of the structure of the device of thepreferred embodiments and operations thereof will be described.

<1-1. Image Compression Device>

FIG. 2 is a block diagram showing an outline of the structure of animage compression device 100 in the preferred embodiment. Picturesignals of three components corresponding to the three components in theRGB (Red, Green, Blue) colorimetric system, for example, aresimultaneously inputted to an image data input interface 300 provided inthis image compression device 100. Each picture signal is formed of 8bits to represent density of a single color component at 256 gradations,for example.

Divided clock signal CLKd generated in a clock divider 400 is suppliedto the image data input interface 300. This clock divider 400 receivesthe clock signal CLK which is a periodic pulse train inputted from theclock input terminal 1, divides the signal CLK by 1/3, and provides theobtained divided clock signal CLKd to the image data input interface 300as an input. That is, a pulse train having a period which is three timesthat of the clock signal CLK is supplied to the image date inputinterface 300.

In the image date input interface 300, the inputted picture signals aresequentially inputted to the image data input interface 300 from anexternal device through an image data input terminal 2 having a widthcorresponding to 8 bits×3 inputs in synchronization with the dividedclock signal CLKd. That is to say, in synchronization with the pulsetrain with a period three times that of the clock signal CLK, thepicture signals corresponding to three components are simultaneouslysupplied as inputs to the image data input interface 300.

In the image data input interface 300, the train of inputted picturesignals corresponding to the three components are respectively dividedfor each block with 8×8 (=64) picture elements arranged in a matrixalong two perpendicular scanning directions on the image, for example,and they are outputted to an encoder (coding unit) 200 on the nextstage. This operation is made in synchronization with the clock signalCLK. That is, picture signals which belong to any of the components orany of the blocks are sequentially sent to the encoder 200 from theimage data input interface 300 in synchronization with the clock signalCLK, and the component or block to which the sent picture signals belongsequentially changes for every 64 picture signals, for example.

The encoder 200 is configured identically to a device for coding a trainof picture signals corresponding to one component in one block unit insynchronization with the clock signal CLK. The coded signals obtained bythe encoder 200 are sent out to an external storage device or a hostcomputer etc. connected to an output terminal 30 through a host businterface 500.

A control unit 600 serves to control operation of respective deviceunits in synchronization with the clock signal CLK. Its most importantoperation is to send a control signal CONT to make control so that theimage date input interface 300 provides the train of picture signals ina predetermined order to the encoder 200 in synchronization with theclock signal CLK, and to send a selection signal SEL to select adivision value in the clock divider 400.

The clock divider 400 provides a plurality of divided clock signals CLKdwith different division values as outputs on the basis of the selectionsignal SEL from the control unit 600. The control unit 600 sends theselection signal SEL to the clock divider 400 to adequately select oneof the plural kinds of division values depending on the number ofcomponents inputted to the image data input interface 300.

That is to say, if the number of components inputted to the image datainput interface 300 is 3, the 1/3 division value is selected as statedabove, and if the number of the components is 2, a 1/2 division value isselected, and if the number of the component is 1, the clock signal CLKwhich is not divided is outputted as a divided clock signal CLKd as itis.

The divided clock signal CLKd is sent through a clock output terminal 11to the external device connected to the image data input terminal 2.That is done to synchronize the operation of the external device withthe divided clock signal CLKd to enable the picture signals to beinputted to the image data input terminal 2 in synchronization with thedivided clock signal CLKd.

Coding is performed in the encoder 200 so that the size of the codedsignal provided as output from the output terminal 30 to the hostcomputer or the like is smaller than the size of the picture signalinputted to the image data input interface 300 or the encoder 200. Thatis to say, this device 100 realizes compression of picture signals.Further, as the picture signals are inputted to the image data inputinterface 300 in synchronization with the divided clock signal CLKd withits period longer than that of the clock signal CLK with which theoperation of the encoder 200 is synchronized depending on the number ofinput components, the picture signals which belong to a plurality ofcomponents are inputted at the same time in matching with operation ofthe encoder 200.

That is to say, picture signals which belong to a plurality ofcomponents are inputted simultaneously to the image data input interface300, and the number of input picture signals per unit time is maintainedto be the same as the number of picture signals processed by the encoder200 per unit time. Accordingly, the picture signals which belong to aplurality of components are inputted to the image data input interface300 at the same time without wastefully accumulating picture signals inthe image data input interface 300, and without producing wastefulquiescent period in the encoder 200.

Furthermore, as the division value of the divided clock signal CLKd isselected depending on the number of input components by operation of thecontrol unit 600 and the clock divider 400, picture signals which belongto desired number of components can be inputted in the range of 1 to 3components.

<1-2. Image Expansion Device>

To reproduce images, picture signals must be reversely reconstructedfrom the coded signals. An image expansion device which makes a pairwith the device shown in FIG. 2 is used for this purpose. FIG. 3 is ablock diagram showing outline of the structure of an image expansiondevice 101 of the preferred embodiment.

As shown in FIG. 3, coded signals are provided as inputs to a decoder(decoding device unit) 201 from the external host computer or the likeconnected to an input terminal 32 through a host bus interface 501. Thedecoder 201 reconstructs the coded signals into a train of picturesignals in a block unit according to procedure opposite to that of theencoder 200 in synchronization with the clock signal CLK. Thereconstructed picture signals are sequentially sent to an image dataoutput interface 301 in synchronization with the clock signal CLK.

The image data output interface 301 portions out the inputted devicesignals to a plurality of components and simultaneously outputs thepicture signals which belong to the respective components insynchronization with the divided block signal CLKd supplied from theclock divider 400. These output picture signals are sent out to theexternal device through an image data output terminal 33 having a width8 bits×3 outputs.

The control unit 601 controls operation of each device unit insynchronization with the clock signal CLK, and particularly, it send acontrol signal CONT to make control so that the image data outputinterface 301 is supplied with the train of picture signals in apredetermined order from the decoder 201 in synchronization with theclock signal CLK. The control unit 601 also sends out a selection signalSEL for selecting a division value in the clock divider 400.

If the number of components outputted from the image data outputinterface 301 is 3, the 1/3 division value is selected, and if thenumber of the components is 2, the 1/2 division value is selected, andif the number of the component is 1, the clock signal CLK which is notdivided is outputted as the divided clock signal CLKd as it is.

The divided clock signal CLKd is sent through a clock output terminal 31to the external device connected to the image data output terminal 33.This is done to synchronize the operation of the external device withthe divided clock signal CLKd to enable the picture signals to beinputted to the external device in synchronization with the dividedclock signal CLKd.

As the image expansion device 101 operates as described above,compressed coded signals are reconstructed into picture signals. That isto say, this device 101 realizes expansion of coded signals. Further, asthe picture signals are outputted from the image data output interface301 in synchronization with the divided clock signal CLKd with itsperiod longer than that of the clock signal CLK with which the operationof the decoder 201 is synchronized depending on the number of outputcomponents, picture signals which belong to a plurality of componentsare applied as outputs at the same time in matching with operation ofthe decoder 201.

That is to say, picture signals which belong to a plurality ofcomponents are outputted simultaneously from the image date outputinterface 301, and the number of output picture signals per unit time ismaintained to be the same as the number of picture signals processed bythe decoder 201 per unit time. Accordingly, the picture signals whichbelong to a plurality of components are supplied as outputs from theimage data output interface 301 at the same time without wastefullyaccumulating picture signals in the image data output interface 301, andwithout producing wasteful quiescent period in the encoder 200.

Furthermore, as the division value of the divided clock signal CLKd isselected depending on the number of output components by operation ofthe control unit 601 and the clock divider 400, picture signals whichbelong to desired number of components can be outputted in the range of1 to 3 components.

<1-3. Combination of Two Devices>

In normal operation, it is premised that the coded signals are expandedinto picture signals when used. Accordingly, in normal use, both of theimage compression device and the image expansion device are used. FIG. 4shows an example of an image conversion device having both functions forthis purpose. This image conversion device 102 has both the imagecompression device 100 and the image expansion device 101. The codedsignals are supplied as inputs to or outputs from the external hostcomputer or the like connected to an input/output terminal 34 through ahost bus interface 502.

A control unit 602 has both functions of the above-described controlunit 600 and the control unit 601. This device 102 can also performinput and output of picture signals for a plurality of components at thesame time without any additionally provided buffer.

In the image compression device described above, the maximum number ofinput components to the image data input interface 300 is 3, butgenerally the same effect can be produced if it is plural not less than2. For example, if the maximum number of input components is 4, input ofpicture signals can be made at the same time for components in the rangeof 1 to 4. The same is true in the image expansion device.

Further, it is also possible to set the maximum number of inputcomponents to the image data input interface 300 to 1 and have the clockdivider 400 capable of outputting a plurality of divided clock signalsCLKd. In such a device, if the division value of the divided clocksignal CLKd is selected to 1/2, for example, the speed of input ofpicture signals to the image data input interface 300 can be made twotimes slower.

At this time, a quiescent period equivalent to operation period occursin the encoder 200 every time picture signals for one block areprocessed, but the coding process is normally performed in the operationperiod. That is to say, it is advantageous in that operation of theexternal device and operation of the image compression device match eachother without requiring an additional interface provided therebetweenwhen the speed of sending out picture signals in the external deviceconnected to the image data input terminal 2 is two times slower thanthat in the image compression device.

As described above, even if the image data input interface 300 has onlyone input, matching can be established with an external device withslower processing speed by providing the clock divider 400. The same istrue in the image decoding device.

Detailed examples of structures of the image conversion device brieflydescribed above will now be described below. In the figures newly quotedbelow, the same portions as those in the conventional devices shown inFIG. 16 and FIG. 17, and the same portions as those in the devices ofthe preferred embodiment roughly shown in FIGS. 2 thorough 4 aredesignated at the same reference characters and detailed descriptionsthereof are not repeated.

2. First Preferred Embodiment

FIG. 1 is a block diagram showing the structure of an image compressiondevice in this preferred embodiment. In this device 110, the encoder 200performs the JPEG algorithm in the same way as the conventional devicedepicted in FIG. 16. An image data input interface 310, a clock divider410 and a control unit 610 are constructed as examples of the image dateinput interface 300, the clock divider 400 and the control unit 600 inthe image compression device 100, respectively. Accordingly, descriptionon the features in structure and operation discussed on the imagecompression device 100 are not repeated.

The clock divider 410 has a 1/2 divider 411 for 1/2-dividing the clocksignal CLK inputted from the clock input terminal 1 and a 1/3 divider412 for 1/3 dividing the same, where output of each divider is providedas input to a selector 413 together with the clock signal CLK. Theselector 413 selects one of these three kinds of clock signals on thebasis of the selection signal SEL sent from the control unit 610 andoutputs it as a divided clock signal CLKd to the image data inputinterface 310 and the clock output terminal 11.

FIG. 5 shows an internal block diagram of the image data input interface310. As shown in FIG. 5, the image data input interface 310 is providedwith one register and two RAMs for each component. Registers 350, 351and 352 operate in synchronization with the divided clock signal CLKd tohold the picture signal inputted from the image data input terminal 2.

The picture signals held in the register 350 are portioned out to twoRAMs 360a and 360b and stored therein. Similarly, the picture signalsheld in the register 351 are portioned out to and stored in two RAMs361a and 361b, and the picture signals held in the register 352 areportioned out to and stored in two RAMs 362a and 362b.

The six RAMs all have common structure and the same memory size. In theRAM 360a, when an active signal (a low level voltage) is inputted to awrite permission terminal WEC (when write enable), a picture signalinputted to an input terminal D is stored in a memory address specifiedby an address signal A0a inputted to an address terminal A. When anactive signal (a low level voltage) is inputted to a read permissionterminal OEC (when read enable), the picture signal stored in the memoryaddress specified by the address signal A0a inputted to the addressterminal A is provided as output from an output terminal Q. The same istrue in the remaining five RAMs.

The relation among input signals to the write permission terminal WEC,the read permission terminal OEC and an element selection terminal CECand operation of the RAM is shown in FIG. 6. In FIG. 6, the character"L" indicates a low level voltage, the character "H" indicates a highlevel voltage and the character "Hi-Z" indicates that the outputterminal Q is at the high impedance. The character "X" indicates thatthe operation of the RAM does not depend on the level of signal inputtedto the terminals. In the image data input interface 310 shown in FIG. 5,the active signal (the low level voltage) is always inputted to theelement selection terminal CEC in any of the RAMs.

Referring to FIG. 5 again, address signals (A0a-A2a and A0b-A2b) areinput to the six RAMs, write permission signals (WC0a-WC2a andWC0b-WC2b) are input to the write permission terminals WEC and readpermission signals (OC0a-OC2a and OC0b-OC2b) are input to the readpermission terminals OEC form the control signal CONT output from thecontrol unit 610.

FIG. 7 shows a timing chart of these signals forming the control signalCONT. The timing chart of FIG. 7 describes the operation of the presentinvention when picture signals of three components are input to theimage data input interface 310. Also, using the divided clock signalCLKd is obtained by dividing the clock signal CLK by 1/3 using the clockdivider 410.

As depicted in FIG. 7, write enable is specified alternately between thethree RAMs 360a-362a and other three RAMs 360b-362b for each period inwhich 64 picture signals constituting one block are inputted (referredto as a "block period" herein), i.e., for every 64 periods of thedivided clock signal CLK. That is to say, the picture signals arewritten alternately in the three RAMs 360a-362a and other three RAMs360b-362b for each block period.

On the other hand, one of the six RAMs 360a-362a, 360b-362b sequentiallyattains read enable for each 1/3 block period which is obtained by3-dividing a block period, i.e., for every 64 period of the clock signalCLK. Furthermore, write enable and read enable are not specifiedsimultaneously in any of the RAMs 360a-362a, 360b-362b. That is to say,one of the six RAMs is sequentially selected for every 64 periods of theclock signal CLK and the picture signal is read out.

When write enable is specified for each RAM 360a-362a, 360b-362b, theaddress signal changes in synchronization with the divided clock signalCLKd, so that the picture signal is written in synchronization with thedivided clock signal CLKd. When read enable is specified, the addresssignal changes in synchronization with the clock signal CLK, so that thepicture signal is read in synchronization with the clock signal CLK.

That is to say, the picture signals are always written into any of thetwo RAMs sequentially in synchronization with the divided clock signalCLK for each component, and the picture signals are always read insynchronization with the clock signal CLK from any of the six RAMs.Furthermore, in read of the picture signals, the component is changed ina block unit.

As the image data input interface 310 operates as discussed above,picture signals of three components can be inputted simultaneously whilematching is maintained with operations of device units constituting theencoder 200 such as the discrete cosine transform unit 4 operating insynchronization with the clock signal CLK. Accordingly, this device 110is suitable for compression of picture signals of the RGB colorimetricsystem, for example.

Also, as the control unit 610 and the clock divider 410 work to selectthe division value of the divided clock signal CLKd depending on thenumber of input components, picture signals which belong to desirednumber of components in the range of 1 to 3 components can besimultaneously inputted while matching with operation of each deviceunit constituting the encoder 200 is maintained. The control signal CONTsent from the control unit 610 differs depending on the number ofinputted components. For example, if picture signals of two componentsare provided as inputted to the two registers 350 and 351, objects ofcontrol by the control signal CONT are limited to four RAMs 360a, 361a,360b and 361b.

In the timing chart of FIG. 7, an example is shown where thespecification order to address when the picture signals are written inthe RAMs is the same as the specification order when they are read. Inthis case, in the image data input interface 310, inputted picturesignals and outputted picture signals are in the same order. However,the specification order of addresses when the picture signals arewritten in the RAMs and the specification order when they are read canarbitrarily differ. By doing so, it is possible to input picture signalsPm (m=0, 1, . . . ) in a certain order for each block and output thepicture signals Pxy (x, y=0 to 7) to the discrete cosine transform unit4 in an order which does not necessarily coincide with it.

If the picture signals are not inputted in a block unit, that is, ifthey are inputted through a plurality of blocks, a buffer can beprovided on the input side of the image data input interface 310. Thisbuffer is similarly provided in the image data input interface 3 in theconventional device shown in FIG. 16 when the picture signals Pm are notinputted in a block unit to the image data input interface 3, and it isnot a part which is specifically required in this preferred embodiment.

3. Second Preferred Embodiment

FIG. 8 shows the second example of the structure related to the imagedata input interface 300 (FIG. 2). This image date input interface 312corresponds to the case where the component ratio, i.e., the ratio ofthe number of picture elements in each component is 2:1:1. For example,the example of device is suitable for compression of picture signalswhich represent a luminance component Y and two color-differencecomponents U, V in the YUV (YCrCb) colorimetric system respectively with8×16 picture elements, 8×8 picture elements and 8×8 picture elements foreach block. In the description below, assuming that picture signals ofthe YUV colorimetric system having such a component ratio are inputted,the structure and operation of the image date input interface 312 willbe described.

As depicted in FIG. 8, the image date input interface 312 is providedwith one register and four RAMs for the Y component and it is furtherprovided with one register and four RAMs for both the U component andthe V component. While the picture signals of the Y component areinputted for one block, i.e., for 8×16 picture elements, one block ofthe V component (corresponding to 8×8 picture elements) is inputtedfollowing one block of the U component (corresponding to 8×8 pictureelements).

Registers 370 and 371 operate in synchronization with the divided clocksignal CLKd to hold the picture signals inputted from the image dateinput terminal 2. A divided clock signal CLKd obtained by 1/2 dividingthe clock signal CLK is supplied to the image date input interface 312.

The picture signals of the Y components held in the register 370 areportioned out to and stored in the four RAMs 380a-380d. Similarly, thepicture signals of the U component or the V component held in theregister 371 are portioned out to and stored in the four RAMs 381a-381d.The eight RAMs have the same structure as that of the RAM 360a shown inFIG. 5, for example, and the memory size is also the same.

Address signals A0a-A0d, A1a-A1d inputted to the eight RAMs, whilepermission signals WC0a-WC0d, WC1a-WC1d and read permission signalsOC0a-OC0d, OC1a-OC1d form the control signal CONT sent from the controlunit 600 (FIG. 2).

FIG. 9 shows a timing chart of these signals forming the control signalCONT. As depicted in FIG. 9, write enable is specified sequentiallyamong the four RAMs 360a-360d for each period in which 64 picturesignals for one block of the U component or the V component are inputted(referred to as a "block period" herein), i.e., for every 64 periods ofthe divided clock signal CLKd. Accordingly, the picture signal of the Ycomponent are sequentially portioned out and written in the four RAMs360a-360d for every sixty-four.

Similarly, for each block period, write enable is specified sequentiallyamong the four RAMs 361a-361d. Accordingly, 64 picture signals of the Ucomponent and 64 picture elements of the V component are alternately,and sequentially portioned out into the four RAMs 361a-361d, and storedtherein.

On the other hand, in reading picture signals, one of the eight RAMs360a-360d, 361a-361d sequentially attains read enable for each 1/2 blockperiod which is obtained by 2-dividing a block period, i.e., for every64 periods of the clock signal CLK. Furthermore, write enable and readenable are not specified simultaneously in any of the RAMs 360a-360d,361a-361d. That is to say, one of the eight RAMs is sequentiallyselected for every 64 periods of the clock signal CLK and picture signalis read out.

When write enable is specified for each RAM 360a-360d, 361a-361d, theaddress signal changes in synchronization with the divided clock signalCLKd, so that the picture signal is written in synchronization with thedivided clock signal CLKd. When read enable is specified, the addresssignal changes in synchronization with the clock signal CLK, so that thepicture signal is read in synchronization with the clock signal CLK.

That is to say, the picture signals are always written sequentially intoany of the four RAMs in synchronization with the divided clock signalCLKd for each component, and the picture signals are always read insynchronization with the clock signal CLK from any of the eight RAMs.

As the image data input interface 312 operates as discussed above,picture signals which belong to a plurality of components having thecomponent ratio of 2:1:1 can be inputted simultaneously while matchingis maintained with operations of device units constituting the encoder200 such as the discrete cosine transform unit 4 operating insynchronization with the clock signal CLK.

As can be clearly seen from the description above, this image data inputinterface 312 is also an example of the image date input interface 300used to compress picture signals of two components in which 8×16 pictureelements form one block.

4. Third Preferred Embodiment

FIG. 10 is a block diagram showing the structure of an image expansiondevice which forms a pair with the image compression device 100 of thefirst preferred embodiment. In this image expansion device 111, thecoded signals Hn (n=0, 1, . . . ) are sequentially subjected tooperations the same as those in the conventional device shown in FIG. 17in synchronization with the clock signal CLK to be reconstructed intothe picture signals Pxy (x, y=0 to 7). The reconstructed picture signalsPxy are sequentially inputted to an image data outpult interface 311 insynchronization with the clock signal CLK.

FIG. 11 shows an internal block diagram of the image data outputinterface 311. As shown in FIG. 11, the image data output interface 311is configured as if inputs and outputs are exchanged in the image datainput interface 310 shown in FIG. 5. The control signal CONT sent outfrom a control unit 611 is provided at the same timing as in the imagedata input interface 310 as to the address signals A0a-A2a, A0b-A2b, andit is provided at a timing opposite to the signals in the image datainput interface 310 as to the write permission signals WC0a-WC2a,WC0b-WC2b and the read permission signals OC0a-OC2a, OC0b-OC2b.

As the image data output interface 311 is formed as described above andthe control signals are provided at such timings, the image data outputinterface 311 performs operations opposite to those of the image datainput interface 310. That is to say, the image data output interface 311portions out the picture signals Pxy (x, y=0 to 7) inputted insynchronization with the clock signal CLK to picture signals Pm (m=0, 1,. . . , 63) which belongs to each of components and simultaneouslyoutputs the picture signals Pm (m=0, 1, . . . , 63) which belong to therespective components in synchronization with the divided clock signalCLKd.

As discussed above, this image expansion device 111 can simultaneouslyoutput picture signals of three components while maintaining matchingwith operations of device units forming the decoder 201 such as theinverse discrete cosine transform unit 24 which operates insynchronization with the clock signal CLK. Further, the control unit 611and the clock divider 410 work to select division value of the dividedclock signal CLKd depending on the number of output components, so thatit can simultaneously output picture signals which belong to desirablenumber of components in the range of 1 to 3 components while maintainingmatching with operation of the decoder 201.

Also, the image expansion device 111 and the above-described imagecompression device 110 can be combined similarly to the device 102 shownin FIG. 4 to form an image conversion device capable of performing bothcompression and expansion.

5. Fourth Preferred Embodiment

FIG. 12 is a block diagram showing another example of an imagecompression device. This image compression device 120 ischaracteristically different from the image compression device 100 shownin FIG. 1 in that the maximum number of components which can be inputtedto an image data input interface 320 is 4. Accordingly, a clock divider420) further includes a 1/4 divider 415, and a selector 416 selects oneof the four kinds of clock signals on the basis of the selection signalSEL sent from a control unit 620 to provide it to the image data inputinterface 320 and the clock output terminal 11 as the divided clocksignal CLKd.

Though not shown in the figure, the image data input interface 320includes one register and two RAMs for each component similarly to theimage data input interface 310 shown in FIG. 5. That is to say, theimage data input interface 320 has such structure as the structure ofthe image data input interface 310 additionally provided with a registerand RAMs for one more component.

As a result, picture signals which belong to desired number ofcomponents can be inputted at the same time in the range of 1 to 4components while matching with operations of respective device unitsforming the encoder 200 such as the discrete cosine transform unit 4 ismaintained. Also, as this image compression device 120 is capable ofsimultaneous input of four components, it is suitable for compression ofpicture signals of the YMCK calorimetric system, for example.

6. Fifth Preferred Embodiment

FIG. 13 is a block diagram showing still another example of an imagecompression device. This image compression device 130 ischaracteristically different from the image compression device 100 shownin FIG. 1 in that the number of components capable of being input to animage data input interface 330 is fixed to 1. Though not shown in thefigure, the image data input interface 330 includes those for only onecomponent in the image data input interface 310 shown in FIG. 5.

This image compression device 130 is provided with a clock divider 410configured in the same way as that of FIG. 1, where one of three kindsof clock signals is selected on the basis of the selection signal SELsent from a control unit 630 and it is supplied to the image data inputinterface 330 as a divided clock signal CLKd. Accordingly, if thedivision value of the divided clock signal CLKd is selected to 1/2, forexample, speed of input of picture signals to the image data inputinterface 330 can be slowed down by two times. If the division value ofthe divided clock signal CLKd is selected to 1/3, the speed of input ofpicture signals to the image data input interface 330 can be slowed downby three times.

When the division value of the divided clock signal CLKd is 1/2, aquiescent period equivalent to the operation period occurs every timepicture signals for one block are processed in the device units formingthe encoder 200 such as the discrete cosine transform unit 4, and whenthe division value of the divided clock signal CLKd is 1/3, a quiescentperiod two times as long as the operation period occurs. However, codingprocess is normally performed in each operation period.

That is to say, in the case where the speed of sending picture signalsin the external device connected to the image data input terminal 36 istwo or three times slower than in the image compression device,operation of the external device and operation of the image compressiondevice match without requiring an additional interface therebetween.Further, in this image compression device 130, as the control unit 630sends the selection signal SEL corresponding to the speed of sending thepicture signals in the external device to adequately select one ofplural kinds of periods of the divided clock signals CLKd, it isadvantageous in that connection can be made easily with external deviceswith various speeds.

7. Sixth Preferred Embodiment

In FIG. 14, the encoder 200 in the image compression device 100 may beconstructed to perform coding based on other algorithms in place ofperforming the coding based on the JPEG algorithm. For example, it maybe constructed on the basis of the FBTC (Fixed Block Truncation Coding),of which structure is briefly shown in the block diagram of FIG. 14.Detailed description of this algorithm is not given herein because thisalgorithm itself is well known.

As a matter of fact, the decoder 201 in the image expansion device 101may be constructed so as to perform coding other than the JPEGalgorithm. For example, as roughly shown in the block diagram of FIG.15, a decoder may be formed which makes a pair with the encoder shown inFIG. 14 on the basis of the FBTC.

While the invention has been shown and described in detail, theforegoing description is in all aspects illustrative and notrestrictive. It is therefore understood that numerous modifications andvariations can be devised without departing the scope of the invention.

What is claimed is:
 1. The image conversion device for coding a seriesof picture signals representing an image using a number of components,said series of picture signals being partitioned into at least oneblock, the image conversion device comprising:dividing means fordividing a clock signal received from an exterior of the imageconversion device to produce a divided clock signal having a periodwhich is longer than a period of the clock signal; interface means forreceiving said picture signals as inputs in synchronization with saiddivided clock signal produced by said dividing means and forsequentially outputting said picture signals in synchronization withsaid clock signal; and coding means for sequentially receiving as saidpicture signals outputted from said interface means and for convertingsaid picture signals into coded signals in units of blocks, wherein saidinterface means comprises:a receiver for simultaneously receiving pluralcomponents of the number of components equal in number to a ratiobetween the period of the divided clock signal and the period of theclock signal; and an output for sequentially outputting said picturesignals to said coding means in synchronization with said clocksignal,wherein said interface means further comprises:first and secondstorage means for each of the components, each of said first and secondstorage means capable of being read from and written to and including astorage capacity for storing one block of one of the components of saidpicture signals, each of said first storage means and each of saidsecond storage means alternately receiving a different one of thecomponents simultaneously and in synchronization with said divided clocksignal, said first and second storage means writing to said coding meansalternately, in succession, and in synchronization with said clocksignal, one of said first storage means writing to said coding meanswhen each of said second storage means is being written tosimultaneously and one of said second storage means writing to saidcoding means when each of said first storage means is being written tosimultaneously.
 2. The image conversion device according to claim 1,wherein each of said first and second storage means includes a pluralityof unit storage means, and said picture signals for one block are storedover the plurality of unit storage means.
 3. The image conversion deviceaccording to claim 1, wherein the number of the number of components isthree, andwherein each of the number of components belongs to onecomponent of a trichromatic system.
 4. The image conversion deviceaccording to claim 1, wherein said coding means includes compressionmeans for performing coding so that a size of said coded signals issmaller than a size of said picture signals.
 5. The image conversiondevice according to claim 4, wherein said compression means performscoding according to a JPEG algorithm.
 6. An image conversion device forcoding a series of picture signals representing an image using a numberof components, said series of picture signals being partitioned into atleast one block, the image conversion device comprising:dividing meansfor dividing a clock signal received from an exterior of the imageconversion device to produce a divided clock signal having a periodwhich is longer than a period of the clock signal; interface means forreceiving said picture signals as inputs in synchronization with saiddivided clock signal produced by said dividing means and forsequentially outputting said picture signals in synchronization withsaid clock signal; and coding means for sequentially receiving as saidpicture signals outputted from said interface means and for convertingsaid picture signals into coded signals in units of blocks, wherein saidinterface means comprises:a receiver for simultaneously receiving pluralcomponents of the number of components equal in number to a ratiobetween the period of the divided clock signal and the period of theclock signal; an output for sequentially outputting said picture signalsto said coding means in synchronization with said clock signal; and acontrol means for outputting a control signal to the dividing means, thecontrol signal indicating the number of the number of components bywhich the clock signal is to be divided, the number of the number ofcomponents being a natural number greater than 2, wherein said dividingmeans comprises:a plurality of dividers smaller by one in number thanthe number of the number of components, said plurality of dividers saidclock signal into a plurality of divided signals by dividing by naturalnumbers between two and the number of the number of components andoutputting the plurality of divided signals; and signal selection meansfor selecting one of said plurality of divided signals based on saidcontrol signal and for outputting the selected one of the plurality ofdivided signals as said divided clock signal.
 7. The image conversiondevice for decoding coded signals obtained by coding a series of picturesignals representing an image coded using a number of components saidseries of picture signals being partitioned into at least one block, theimage conversion device comprising:decoding means for decoding andconverting said coded signals into said picture signals in units ofblocks and for sequentially outputting said picture signals insynchronization with a clock signal received from an exterior of theimage conversion device; dividing means for dividing said clock signalto produce a divided clock signal having a period which is longer than aperiod of the clock signal; and interface means receiving as inputs saidpicture signals sequentially output by said decoding means andoutputting said picture signal in synchronization with said dividedclock signal, wherein said interface means comprises interface meansreceiving as inputs said picture signals sequentially output by saiddecoding means and simultaneously outputting plural components of thenumber of components equal to a ratio between the period of the dividedclock signal and the period of the clock signal in synchronization withsaid divided clock signal, wherein said interface means furthercomprises:first and second storage means for each of the components,each of said first and second storage means capable of being read fromand written to and including a storage capacity for storing one block ofone of the components of said picture signals, each of said firststorage means and each of said second storage means alternatelyoutputting a different one of the components of said picture signalssimultaneously and in synchronization with said divided clock signal,said first and second storage means being written to by said decodingmeans alternately, in succession and in synchronization with said clocksignal, one of said first storage means being written to by saiddecoding means when each of said second storage means are outputting acorresponding one of the components simultaneously and one of saidsecond storage means being written to by said decoding means when eachof said first storage means are outputting the corresponding one of thecomponents simultaneously.
 8. The image conversion device of claim 7,wherein each of said first and second storage means includes a pluralityof unit storage means, and said picture signals for one block are storedover the plurality of unit storage means.
 9. The image conversion deviceaccording to claim 7, wherein the number of the number of components isthree, andwherein each of the number of components belongs to onecomponent of a trichromatic system.
 10. The image conversion deviceaccording to claim 7, wherein said coded signal is a compressed signalhaving a size smaller than a size of said picture signal, andwhereinsaid decoding means includes an expansion means for expanding said codedsignal.
 11. The image conversion device according to claim 10, whereinsaid expansion means performs decoding according to a JPEG algorithm.12. An image conversion device for decoding coded signals obtained bycoding a series of picture signals representing an image coded using anumber of components, said series of picture signals being partitionedinto at least one block the image conversion device comprising:decodingmeans for decoding and converting said coded signals into said picturesignals in units of blocks and for sequentially outputting said picturesignals in synchronization with a clock signal received from an exteriorof the image conversion device; dividing means for dividing said clocksignal to produce a divided clock signal having a period which is longerthan a period of the clock signal; and interface means receiving asinputs said picture signals sequentially output by said decoding meansand outputting said picture signal in synchronization with said dividedclock signal; and a control means for outputting a control signal to thedividing means the control signal indicating the number of the number ofcomponents by which the clock signal is to be divided wherein the numberof the number of components is a natural number greater than 2, whereinsaid interface means comprises interface means receiving as inputs saidpicture signals sequentially output by said decoding means andsimultaneously outputting plural components of the number of componentsequal to a ratio between the period of the divided clock signal and theperiod of the clock signal in synchronization with said divided clocksignal, and wherein said dividing means comprises:a plurality ofdividers smaller by one in number than the number of the number ofcomponents, said plurality of dividers dividing said clock signal into aplurality of divided signals by dividing by natural numbers between twoand the number of the number of components and outputting the pluralityof divided signals; and signal selection means for selecting one of saidplurality of divided signals based on said control signal and foroutputting the selected one of the plurality of divided signals as saiddivided clock signal.
 13. The image conversion device capable of codinga series of picture signals, representing an image using a number ofcomponents, into coded signals and capable of decoding the coded signalsinto said picture signals, said picture signals being partitioned intoat least one block, the image conversion device comprising:dividingmeans for dividing a clock signal received from an exterior of the imageconversion device to produce a divided clock signal having a periodwhich is longer than a period of the clock signal; first interface meansfor receiving said picture signals as inputs, in synchronization withsaid divided clock signal produced by. said dividing means, and forsequentially outputting said picture signals in synchronization withsaid clock signal; coding means for sequentially receiving as inputssaid picture signals outputted from said interface means and forconverting said picture signals into said coded signals in units ofblocks; decoding means for decoding and converting said coded signalsinto said picture signals in said units of blocks and for sequentiallyoutputting said picture signals in synchronization with said clocksignal; and second interface means for sequentially receiving as inputssaid picture signals outputted from said decoding means and outputtingsaid picture signals in synchronization with said divided clock signalwherein:the first interface device comprises a receiver forsimultaneously receiving plural components of the number of componentsequal in number to a ratio between the period of the divided clocksignal and the period of the clock signal; and the second interfacedevice comprises an output device for simultaneously outputting theportion of the number of components equal in number to the ratio,wherein said first interface means comprises:first and second storagemeans for each of the components, each of said first and second storagemeans capable of being read from and written to and including a storagecapacity for storing one block of one of the components of said picturesignals, each of said first storage means and each of said secondstorage means alternately receiving a different one of the components ofsaid picture signals simultaneously and in synchronization with saiddivided clock signal, said first and second storage means writing tosaid coding means alternately, in succession, and, in synchronizationwith said clock signal, one of said first storage means writing to saidcoding means when each of said second storage means is being written tosimultaneously and one of said second storage means writing to saidcoding means when each of said first storage means is being written tosimultaneously; and wherein said second interface means comprises:thirdand fourth storage means for each of the components, each of said thirdand fourth storage means capable of being read from and written to andincluding a storage capacity storing one block of one of the componentsof said picture signals, each of said third storage means and each ofsaid fourth storage means alternately outputting a corresponding one ofthe components of said picture signals simultaneously and insynchronization with said divided clock signal, said third and fourthstorage means being written to alternately and in succession by saiddecoding means in synchronization with said clock signal, one of saidthird storage means being written to by said decoding means when each ofsaid fourth storage means is simultaneously outputting a correspondingone of the components, and one of said fourth storage means beingwritten to by said decoding means when each of said third storage meansis simultaneously outputting a corresponding one of the components. 14.The image conversion device according to claim 13, wherein each of saidfirst and second storage means includes a plurality of unit storagemeans, and said picture signals for one block are stored over theplurality of unit storage means.
 15. The image conversion deviceaccording to claim 13, wherein each of said third and fourth storagemeans includes a plurality of unit storage means, and said picturesignals for one block are stored over the plurality of unit storagemeans.
 16. The image conversion device according to claim 13, whereinthe number of the number of components is three, andwherein each of thenumber of components belongs to one component of a trichromatic system.17. The image conversion device according to claim 13, wherein saidcoding means includes compression means for performing coding so that asize of said coded signals is smaller than a size of said picturesignals, andsaid decoding means includes expansion means for expandingsaid coded signals.
 18. The image conversion device according to claim17, wherein said compression means performs coding according to a JPEGalgorithm, and said expansion means performs decoding according to theJPEG algorithm.
 19. An image conversion device capable of coding aseries of picture signals, representing an image using a number ofcomponents, into coded signals and capable of decoding the coded signalsinto said picture signals, said picture signals being partitioned intoat least one block, the image conversion device comprising:dividingmeans for dividing a clock signal received from an exterior of the imageconversion device to produce a divided clock signal having a periodwhich is longer than a period of the clock signal; first interface meansfor receiving said picture signals as inputs, in synchronization withsaid divided clock signal produced by said dividing means, and forsequentially outputting said picture signals in synchronization withsaid clock signal; coding means for sequentially receiving as inputssaid picture signals outputted from said interface means and forconverting said picture signals into said coded signals in units ofblocks; decoding means for decoding and converting said coded signalsinto said picture signals in said units of blocks and for sequentiallyoutputting said picture signals in synchronization with said clocksignal; and second interface means for sequentially receiving as inputssaid picture signals outputted from said decoding means and outputtingsaid picture signals in synchronization with said divided clock signalwherein:the first interface device comprises a receiver forsimultaneously receiving plural components of the number of componentsequal in number to a ratio between the period of the divided clocksignal and the period of the clock signal; the second interface devicecomprises an output device for simultaneously outputting the portion ofthe number of components equal in number to the ratio; and a controlmeans for outputting a control signal to the dividing means, the controlsignal indicating the number of the number of components by which theclock signal is to be divided wherein the number of the number ofcomponents is a natural number greater than 2, wherein said dividingmeans comprises:a plurality of dividers smaller by one in number thanthe number of the number of the components, said plurality of dividersdividing said clock signal into a plurality of divided signals bydividing by natural numbers between two and the number of the number ofcomponents and outputting said plurality of divided signals; and signalselection means for selecting one of said plurality of divided signalsbased on said control signal and for outputting the selected one of theplurality of divided signals as said divided clock signal.
 20. The imageconversion device for coding a series of picture signals representing animage using a number of components, said series of picture signals beingpartitioned into at least one block, the image conversion devicecomprising:dividing means for dividing a clock signal received from anexterior of the image conversion device to produce a divided clocksignal having a period which is longer than a period of the clocksignal; interface means for receiving said picture signals as inputs insynchronization with said divided clock signal produced by said dividingmeans, and for sequentially outputting said picture signals insynchronization with said clock signal; and coding means forsequentially receiving as said picture signals outputted from saidinterface means and for converting said picture signals into codedsignals in units of blocks, wherein said interface means comprises:areceiver for simultaneously receiving plural components of the number ofcomponents equal in number to a ratio between the period of the dividedclock signal and the period of the clock signal; and an output forsequentially outputting said picture signals to said coding means insynchronization with said clock signal, wherein said interface meansfurther comprises:first and second memories for each of the components,each of said first and second memories capable of being read from andwritten to and including a storage capacity for storing one block of oneof the components of said picture signals, each of said first memoriesand each of said second memories alternately receiving a different oneof the components simultaneously and in synchronization with saiddivided clock signal, said first and second memories writing to saidcoding means alternately, in succession, and in synchronization withsaid clock signal, one of said first memories writing to said codingmeans when each of said second memories is being written tosimultaneously and one of said second memories writing to said codingmeans when each of said first memories is being written tosimultaneously.
 21. The image conversion device for decoding codedsignals obtained by coding a series of picture signals representing animage coded using a number of components, said series of picture signalsbeing partitioned into at least one block, the image conversion devicecomprising:decoding means for decoding and converting said coded signalsinto said picture signals in units of blocks and for sequentiallyoutputting said picture signals in synchronization with a clock signalreceived from an exterior of the image conversion device, dividing meansfor dividing said clock signal to produce a divided clock signal havinga period which is longer than a period of the clock signal; andinterface means receiving as inputs said picture signals sequentiallyoutput by said decoding means and outputting said picture signal insynchronization with said divided clock signal, wherein said interfacemeans comprises interface means receiving as inputs said picture signalssequentially output by said decoding means and simultaneously outputtingplural components of the number of components equal to a ratio betweenthe period of the divided clock signal and the period of the clocksignal in synchronization with said divided clock signal, wherein saidinterface means further comprises:first and second memories for each ofthe components, each of said first and second memories capable of beingread from and written to and including a storage capacity for storingone block of one of the components of said picture signals, each of saidfirst memories and each of said second memories alternately outputting adifferent one of the components of said picture signals simultaneouslyand in synchronization with said divided clock signal, said first andsecond memories being written to by said decoding means alternately, insuccession and in synchronization with said clock signal, one of saidfirst memories being written to by said decoding means when each of saidsecond memories are outputting a corresponding one of the componentssimultaneously and one of said second memories being written to by saiddecoding means when each of said first memories are outputting thecorresponding one of the components simultaneously.
 22. The imageconversion device capable of coding a series of picture signals,representing an image using a number of components, into coded signalsand capable of decoding the coded signals into said picture signals,said picture signals being partitioned into at least one block, theimage conversion device comprising:dividing means for dividing a clocksignal received from an exterior of the image conversion device toproduce a divided clock signal having a period which is longer than aperiod of the clock signal; first interface means for receiving saidpicture signals as inputs, in synchronization with said divided clocksignal produced by said dividing means, and for sequentially outputtingsaid picture signals in synchronization with said clock signal; codingmeans for sequentially receiving as inputs said picture signalsoutputted from said interface means and for converting said picturesignals into said coded signals in units of blocks; decoding means fordecoding and converting said coded signals into said picture signals insaid units of blocks and for sequentially outputting said picturesignals in synchronization with said clock signal; and second interfacemeans for sequentially receiving as inputs said picture signalsoutputted from said decoding means and outputting said picture signalsin synchronization with said divided clock signal wherein:the firstinterface device comprises a receiver for simultaneously receivingplural components of the number of components equal in number to a ratiobetween the period of the divided clock signal and the period of theclock signal; and the second interface device comprises an output devicefor simultaneously outputting the portion of the number of componentsequal in number to the ratio, wherein said first interface meanscomprises:first and second memories for each of the components, each ofsaid first and second memories capable of being read from and written toand including a storage capacity for storing one block of one of thecomponents of said picture signals, each of said first memories and eachof said second memories alternately receiving a different one of thecomponents of said picture signals simultaneously and in synchronizationwith said divided clock signal, said first and second memories writingto said coding means alternately, in succession, and, in synchronizationwith said clock signal, one of said first memories writing to saidcoding means when each of said second memories is being written tosimultaneously and one of said second memories writing to said codingmeans when each of said first memories is being written tosimultaneously; and wherein said second interface means comprises:thirdand fourth memories for each of the components, each of said third andfourth memories capable of being read from and written to and includinga storage capacity storing one block of one of the components of saidpicture signals, each of said third memories and each of said fourthmemories alternately outputting a corresponding one of the components ofsaid picture signals simultaneously and in synchronization with saiddivided clock signal, said third and fourth memories being written toalternately and in succession by said decoding means in synchronizationwith said clock signal, one of said third memories being written to bysaid decoding means when each of said fourth memories is simultaneouslyoutputting a corresponding one of the components, and one of said fourthmemories being written to by said decoding means when each of said thirdmemories is simultaneously outputting a corresponding one of thecomponents.